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    首頁產(chǎn)品索引MC100EL35

    MC100EL35

    購買收藏
    ?ECL JK Flip-Flop

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10EL/100EL35 is a high speed JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.
    • 525ps Propagation Delay
    • 2.2GHz Toggle Frequency
    • ESD Protection: > 1 kV HBM, > 100 V MM
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors on J, K, CLK, and R
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94V-0 @ 0.125 in, Oxygen Index: 28 to 34
    • Transistor Count = 81 devices
    • Pb-Free Packages are Available

    在線購買

    型號制造商描述購買
    MC100EL35DGONIC FF D-TYPE SNGL 1BIT 8SOIC 立即購買

    技術資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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