free性丰满hd毛多多,久久综合给合久久狠狠狠97色69 ,欧美成人乱码一区二区三区,国产美女久久久亚洲综合,7777久久亚洲中文字幕

尊敬的客戶：為給您持續(xù)提供一對一優(yōu)質(zhì)服務(wù)，即日起，元器件訂單實付商品金額<300元時，該筆訂單按2元/SKU加收服務(wù)費，感謝您的關(guān)注與支持！
電子產(chǎn)業(yè)一站式服務(wù)平臺
注冊新人禮包
我的訂單
聯(lián)系客服
    首頁產(chǎn)品索引MC100EP142

    MC100EP142

    購買收藏
    ?ECL 9-Bit Shift Register

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10EP/100EP142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in andserial/parallel out, shifting in one direction. The nine inputs D0 - D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.
    The SEL (Select) input pin is used to switch between the two modes of operation - SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the resisters to zero.
    The 100 Series contains temperature compensation.
    • > 3 GHz Minimum Shift Frequency
    • 9-Bit for Byte-Parity Applications
    • Asynchronous Master Reset
    • Dual Clocks
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = –3.0 V to –5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100EP142MNGONIC SHIFT REGISTER 9BIT ECL 32QFN 立即購買
    MC100EP142FAR2GONIC REGISTER SHFT 9BIT ECL 32LQFP 立即購買
    MC100EP142FAGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

    應(yīng)用案例更多案例

    系列產(chǎn)品索引查看所有產(chǎn)品

    MC10EL16MD1715MC10EP08MCP1631
    MCP4801MCP7940NMIC38C45MC100EL31
    MCP23009MJ15016MCT62MC100E131
    MCP23S18MCP9803MCP809MCP37D31-200
    MCP2025MCP9844MCP48FEB21MC74HC273A
    Copyright ?2012-2025 hqchip.com.All Rights Reserved 粵ICP備14022951號工商網(wǎng)監(jiān)認證 工商網(wǎng)監(jiān) 營業(yè)執(zhí)照