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    首頁產(chǎn)品索引MC100EP31

    MC100EP31

    購買收藏
    ?ECL D Flip-Flop with Set and Reset

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10/100EP31 is a D flip-flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.
    The 100 Series contains temperature compensation.
    • 340ps Typical Propagation Delay
    • Maximum Frequency > 3 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V
    • with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V
    • with V
    • = –3.0 V to –5.5 V
    • Open Input Default State
    • Q Output will default LOW with inputs open or at V
    • Pb-Free Packages are Available

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    在線購買

    型號制造商描述購買
    MC100EP31DTR2GONIC FF D-TYPE SNGL 1BIT 8TSSOP 立即購買
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    MC100EP31DTGON 立即購買

    技術(shù)資料

    標題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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