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    首頁產(chǎn)品索引MC100EP52

    MC100EP52

    購買收藏
    ?ECL Differential Clock/Data D Flip-Flop

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to V
    ) the outputs of the device will remain stable.
    • 330ps Typical Propagation Delay
    • Maximum Frequency > 4 GHz Typical
    • PECL Mode: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Q Output will default LOW with inputs open or at V
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購買

    型號(hào)制造商描述購買
    MC100EP52MNR4GON 立即購買
    MC100EP52DTR2GON 立即購買
    MC100EP52DR2GON 立即購買
    MC100EP52DGON 立即購買
    MC100EP52DTGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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