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    首頁(yè)產(chǎn)品索引MC100EP57

    MC100EP57

    購(gòu)買(mǎi)收藏
    1 Differential, ECL, 3.3 V / 5.0 V

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10/100EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EP57 makes it ideal for use in low skew applications such as clock distribution.
    The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0).
    Multiple V
    outputs are provided. The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, V
    should be left open.
    The 100 Series contains temperature compensation.
    • 375 ps Typical Propagation Delays
    • Maximum Frequency > 2 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Q Output will default LOW with inputs open or at V
    • V
    • Outputs
    • Useful as Either 4:1 or 2:1 Multiplexer
    • These are Pb-Free Devices

    電路圖、引腳圖和封裝圖

    在線購(gòu)買(mǎi)

    型號(hào)制造商描述購(gòu)買(mǎi)
    MC100EP57MNGONIC DIFF DIGIT MULTPL 1X4:1 20QFN 立即購(gòu)買(mǎi)
    MC100EP57DTR2GONIC DIFF DIG MULTPL 1X4:1 20TSSOP 立即購(gòu)買(mǎi)
    MC100EP57DTGONIC DIFF DIG MULTPL 1X4:1 20TSSOP 立即購(gòu)買(mǎi)

    技術(shù)資料

    標(biāo)題類(lèi)型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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