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    首頁產(chǎn)品索引MC100EPT21

    MC100EPT21

    購買收藏
    ?Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.
    The V
    output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, V
    output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, V
    output is connected through a resistor to each input pin. If used, the V
    pin should be bypassed to V
    via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use V
    for a single-ended direct connection.
    • 1.4ns Typical Propagation Delay
    • Maximum Frequency > 275 MHz Typical
    • 24mA TTL outputs
    • LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs
    • The 100 Series Contains Temperature Compensation
    • V
    • Output
    • New Differential Input Common Mode Range

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    型號制造商描述購買
    MC100EPT21MNR4GON 立即購買
    MC100EPT21DTR2GON 立即購買
    MC100EPT21DR2GON 立即購買
    MC100EPT21DGON 立即購買
    MC100EPT21DTGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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