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    首頁產(chǎn)品索引MC100LVEL13

    MC100LVEL13

    購買收藏
    3 Differential, Dual ECL, 3.3 V

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer. The MC100EL13 is pin and functionally equivalent to the MC100LVEL13 but is specified for operation at the standard 100E ECL voltage supply. The Low Output-Output Skew of the device makes it ideal for distributing two different frequency synchronous signals.
    The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V
    , The Dbar input will bias around V
    /2 and the Q output will go LOW.
    • 500 ps Typical Propagation Delays
    • 50 ps Output-Output Skews
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Q Output will Default LOW with Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 143 devices

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100LVEL13DWR2GONMC100LVEL13 是一款雙、全差分 1:3 扇出緩沖器。MC100EL13 的引腳和功能與 MC100LVEL13 相當(dāng)，但規(guī)格基于標(biāo)準(zhǔn) 100E ECL 運行電壓電源。該器件的低輸出-輸出歪曲率使其適用于分發(fā)兩個不同頻率的同步信號。這些差分輸入具有特殊電路，可確保開路輸入條件下的器件穩(wěn)定性。兩個差分輸入均保持在開路狀態(tài)時，D 輸入將拉低至 VEE，Dbar 輸入將圍繞 VCC/2 進(jìn)行偏置，Q 輸出則進(jìn)入低電平狀態(tài)。 立即購買
    MC100LVEL13DWGONMC100LVEL13 是一款雙、全差分 1:3 扇出緩沖器。MC100EL13 的引腳和功能與 MC100LVEL13 相當(dāng)，但規(guī)格基于標(biāo)準(zhǔn) 100E ECL 運行電壓電源。該器件的低輸出-輸出歪曲率使其適用于分發(fā)兩個不同頻率的同步信號。這些差分輸入具有特殊電路，可確保開路輸入條件下的器件穩(wěn)定性。兩個差分輸入均保持在開路狀態(tài)時，D 輸入將拉低至 VEE，Dbar 輸入將圍繞 VCC/2 進(jìn)行偏置，Q 輸出則進(jìn)入低電平狀態(tài)。 立即購買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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