free性丰满hd毛多多,久久综合给合久久狠狠狠97色69 ,欧美成人乱码一区二区三区,国产美女久久久亚洲综合,7777久久亚洲中文字幕

尊敬的客戶：為給您持續(xù)提供一對(duì)一優(yōu)質(zhì)服務(wù)，即日起，元器件訂單實(shí)付商品金額<300元時(shí)，該筆訂單按2元/SKU加收服務(wù)費(fèi)，感謝您的關(guān)注與支持！
電子產(chǎn)業(yè)一站式服務(wù)平臺(tái)
注冊(cè)新人禮包
我的訂單
聯(lián)系客服
    首頁產(chǎn)品索引MC100LVEL56

    MC100LVEL56

    購買收藏
    1 Differential, Dual ECL, 3.3 V

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC100LVEL56 is a dual, fully differential 2:1 multiplexer.The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals.
    The device features both individual and common select inputs to address both data path and random logic applications.
    The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V
    .The Dbar input will bias around V
    /2 forcing the Q output LOW.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    • 440ps Typical Propagation Delays
    • Separate and Common Select
    • ESD Protection: >2 KV HBM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input 75 K ohm Pulldown Resistors
    • Q Output will Default LOW with Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 147 devices
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購買

    型號(hào)制造商描述購買
    MC100LVEL56DWGONIC DIFF DIG MULTPL 2X2:1 20SOIC 立即購買
    MC100LVEL56DWR2GONIC DIFF DIG MULTPL 2X2:1 20SOIC 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

    應(yīng)用案例更多案例

    系列產(chǎn)品索引查看所有產(chǎn)品

    MC100EL1648MC10EP105MCP45HV31MRF49XA
    MC14503BMCP3428MCP47A1MMBF5462
    MC74HC373AMCP19114MCP1403MCP616
    MC74LVXT4053MMBFJ270MC74HC1GU04MM74HCT373
    MCP39F511MIC4224MC10E1651MCT61
    Copyright ?2012-2025 hqchip.com.All Rights Reserved 粵ICP備14022951號(hào)工商網(wǎng)監(jiān)認(rèn)證 工商網(wǎng)監(jiān) 營(yíng)業(yè)執(zhí)照