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    首頁(yè)產(chǎn)品索引MC10EP016

    MC10EP016

    購(gòu)買(mǎi)收藏
    ?ECL 8-Bit Synchronous Binary Counter

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10/100EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS family.
    The counter features internal feedback to TCbar gated by the TCLD (Terminal Count Load) pin. When TCLD is LOW (or left open, in which case it is pulled LOW by the internal pulldowns), the TCbar feedback is disabled, and counting proceeds continuously, with TCbar going LOW to indicate an all-one state. When TCLD is HIGH, the TC feedback causes the counter to automatically reload upon TC = LOW, thus functioning as a programmable counter. The Qn outputs do not need to be terminated for the count function to operate properly. To minimize noise and power, unused Q outputs should be left unterminated.
    COUT and COUTbar provide differential outputs from a single, non-cascaded counter or divider application. COUT and COUTbar should not be used in cascade configuration. Only TCbar should be used for a counter or divider cascade chain output.
    A differential clock input has also been added to improve performance.
    The 100 Series contains temperature compensation.
    • 500 ps Typical Propagation Delay
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Internal TCbar Feedback (Gated)
    • Addition of COUT and COUTbar
    • 8-Bit
    • Differential Clock Input
    • V
    • Output
    • Fully Synchronous Counting and TCbar Generation
    • Asynchronous Master Reset
    • Pb-Free Packages are Available

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    在線購(gòu)買(mǎi)

    型號(hào)制造商描述購(gòu)買(mǎi)
    MC10EP016FAR2GON 立即購(gòu)買(mǎi)
    MC10EP016FAGON 立即購(gòu)買(mǎi)

    技術(shù)資料

    標(biāo)題類(lèi)型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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