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    首頁(yè)產(chǎn)品索引MC10EP446

    MC10EP446

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    ?3.3 V / 5.0 V ECL 8-Bit Differential Parallel to Serial Converter

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10/100EP446 is an integrated 8-bit parallel to serial data converter. The device is designed with unique circuit topology to operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence from parallel data into a serial data stream is from bit D0 to D7. The parallel input pins D0-D7 are configurable to be threshold controlled by CMOS, ECL, or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal data rate using the CKSEL pin.
    Control pins are provided to reset (SYNC) and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flip-flops are triggered on the rising edge for CLK and the multiplexers are switched on the falling edge of CLK, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, V
    pin is provided for single-ended input condition.
    The 100 Series devices contain temperature compensation network.
    • 3.2 Gb/s Typical Data Rate Capability
    • Differential Clock and Serial Inputs
    • V
    • Output for Single-ended Input Applications
    • Asynchronous Data Reset (SYNC)
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Parallel Interface Can Support PECL, TTL and CMOS
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC10EP446FAGONMC10/100EP446 是一個(gè)集成的8位并行到串行數(shù)據(jù)轉(zhuǎn)換器。該設(shè)備設(shè)計(jì)具有獨(dú)特的電路拓?fù)?，可支持高達(dá)3.2 Gb/s的數(shù)據(jù)速率。 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載

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