free性丰满hd毛多多,久久综合给合久久狠狠狠97色69 ,欧美成人乱码一区二区三区,国产美女久久久亚洲综合,7777久久亚洲中文字幕

尊敬的客戶：為給您持續(xù)提供一對(duì)一優(yōu)質(zhì)服務(wù)，即日起，元器件訂單實(shí)付商品金額<300元時(shí)，該筆訂單按2元/SKU加收服務(wù)費(fèi)，感謝您的關(guān)注與支持！
電子產(chǎn)業(yè)一站式服務(wù)平臺(tái)
注冊(cè)新人禮包
我的訂單
聯(lián)系客服
    首頁(yè)產(chǎn)品索引NB2309A

    NB2309A

    購(gòu)買收藏
    ?Zero Delay Buffer, 3.3 V, Nine Output

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The NB2309A is a versatile, 3.3 V zero delay buffer designed to distribute high-speed clocks. It accepts one reference input and drives out nine low-skew clocks. It is available in a 16 pin package.
    The -1H version of the NB2309A operates at up to 133 MHz, and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.
    The NB2309A has two banks of four outputs each, which can be controlled by the Select inputs as shown in the Select Input Decoding Table. If all the output clocks are not required, Bank B can be three-stated. The select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes.
    Multiple NB2309A devices can accept the same input clock and distribute it. In this case the skew between the outputs of the two devices is guaranteed to be less than 700 ps.
    All outputs have less than 200 ps of cycle-to-cycle jitter. The input and output propagation delay is guaranteed to be less than 250 ps, and the output to output skew is guaranteed to be less than 250 ps.
    The NB2309A is available in two different configurations, as shown in the ordering information table. The NB2309AI is the base part. The NB2309AI1H is the high drive version of the -1 and its rise and fall times are much faster than -1 part.
    • 15 MHz to 133 MHz Operating Range, Compatible with CPU and PCI Bus Frequencies
    • Zero Input - Output Propagation Delay
    • Multiple Low-Skew Outputs
    • Output-Output Skew Less than 250 ps
    • Device-Device Skew Less than 700 ps
    • One Input Drives 9 Outputs, Grouped as 4 + 4 + 1
    • Less than 200 ps Cycle-to-Cycle Jitter is Compatible with Pentium? Based Systems
    • Test Mode to Bypass PLL
    • Available in 16 Pin, 150 mil SOIC and 4.4 mm TSSOP
    • 3.3 V Operation, Advanced 0.35 μ CMOS Technology
    • Pb-Free Packages

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    NB2309AI1HDTGONIC BUFFER CLK 9OUT 3.3V 16-TSSOP 立即購(gòu)買
    NB2309AI1DGONPLL BASED CLOCK DRIVER, 2309 SER 立即購(gòu)買
    NB2309AI1DTR2GON 立即購(gòu)買
    NB2309AI1HDR2GONIC BUFFER CLK 9OUT 3.3V 16-SOIC 立即購(gòu)買
    NB2309AI1DR2GON 立即購(gòu)買
    NB2309AI1HDTR2GONIC BUFFER CLK 9OUT 3.3V 16-TSSOP 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    Zero Delay Buffer, 3.3 V, Nine OutputPDF83 點(diǎn)擊下載
    IBIS Model for NB2309AI1HDT high driveUNKNOW50 點(diǎn)擊下載
    IBIS Model for nb2309ai1dt standard driveUNKNOW19 點(diǎn)擊下載
    SOIC 16 LEADPDF37 點(diǎn)擊下載
    TSSOP-16PDF40 點(diǎn)擊下載
    NB2309A_PKG.GIFUNKNOW9 點(diǎn)擊下載

    應(yīng)用案例更多案例

    系列產(chǎn)品索引查看所有產(chǎn)品

    NCV7344NCL30105NB3M8302CNB4L7210
    NCV8440ANCP2993NCP1565NB3N201S
    NC7S02NC7SZ374NUD4011NCP398
    NVMFS5A140PLZNCV33164NUD4001NCP1341
    NSVR351SDSA3NUF6402NUD4700NCV70501
    Copyright ?2012-2025 hqchip.com.All Rights Reserved 粵ICP備14022951號(hào)工商網(wǎng)監(jiān)認(rèn)證 工商網(wǎng)監(jiān) 營(yíng)業(yè)執(zhí)照