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    首頁(yè)產(chǎn)品索引NBSG53A

    NBSG53A

    購(gòu)買收藏
    ?2.5 V / 3.3 V Selectable Differential Clock / Data D Flip-Flop / Clock Divider with Reset and OLS

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The NBSG53A is a multi-function differential D flip-flop (DFF) or fixed divide by 2 (DIV/2) clock generator. This is part of the GigaComm family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) package.
    The NBSG53A is a device with data, clock, OLS, reset, and select inputs. Differential inputs incorporate internal 50-ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CMOS, CML, or LVDS. The OLS input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single-ended and can be driven with either LVECL or LVCMOS input levels.
    Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG53A allow the device to also be used as a negative edge triggered device.
    • Maximum Input Clock Frequency (DFF) > 8 GHz Typical
    • Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
    • 210 ps Typical Propagation Delay (OLS = FLOAT)
    • 45 ps Typical Rise and Fall Times (OLS = FLOAT)
    • Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak-to-Peak Output)
    • 50 Ω Internal Input Termination Resistors on all Differential Input
    • DIV/2 Mode (Active with Select Low)
    • D Flip Flop Mode (Active with Select High)
    • Selectable Swing PECL Output with Operating Range: V
    • = 2.375 V to 3.465 V with V
    • = 0 V
    • Selectable Swing NECL Output with NECL Inputs with Operating Range: V
    • = 0 V with V
    • = -2.375 V to -3.465 V

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

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    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載
    Thermal Analysis and Reliability of WIRE BONDED ECLPDF119 點(diǎn)擊下載

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