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    首頁產(chǎn)品索引MC100EP140

    MC100EP140

    購買收藏
    ?Phase-Frequency Detector, 3.3 V, ECL

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC100EP140 is a three state phase frequency-detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Since the part is designed with fully differential gates, the noise is reduced throughout the circuit, especially at high speeds. The basic operation of a Phase/Frequency Detector (PFD) is to "compare" an incoming signal (feedback) to a set reference signal. When the Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase, the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO.
    The device is packaged in a small outline, surface mount 8-lead SOIC package. The output of the EP140 is 400 mV, which allows faster switching time and greater bandwidth. This device can also be used in +3.3 V systems. For proper operation, the input edge rate of the R and FB inputs should be less than 5 ns.
    More information on Phase Lock Loop operation and application can be found in AND8040.
    • 500 ps Typical Propagation Delay
    • Maximum Frequency > 2.1 Ghz Typical
    • Fully Differential Internally
    • Advanced High Band Output Swing of 400 mV
    • Transfer Gain: 1.0 mV/Degree at 1.4 GHz, 1.2 mV/Degree at 1.0 GHz
    • Rise and Fall Time: 100 ps Typical
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.6 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.6 V
    • Open Input Default State
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

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    型號(hào)制造商描述購買
    MC100EP140DR2GONMC100EP140 是一款三態(tài)相位頻率檢測(cè)器，用于在鎖定時(shí)需要最低相位和頻率差的相鎖定環(huán)路應(yīng)用。由于該零部件采用全差分門極設(shè)計(jì)，因此降低了整個(gè)電路的噪聲，特別是在高速時(shí)。相位/頻率檢測(cè)器（PFD）的基本操作是將輸入信號(hào)（反饋）與設(shè)置的參考信號(hào)進(jìn)行“比較”。參考 (R) 和反饋 (FB) 輸入的頻率和/或相位不同時(shí)，差分 UP (U) 和 DOWN (D) 輸出將提供脈沖流，如果減去和集成這些脈沖流則會(huì)提供用于控制 VCO 的誤差電壓。該器件采用小型表面貼裝 8 引線 SOIC 封裝。EP140 的輸出為 400 mV，可實(shí)現(xiàn)更快的切換時(shí)間和更大的帶寬。此器件還可用于 +3.3 V 系統(tǒng)。為了正確操作，R 和 FB 輸入的輸入邊沿速率應(yīng)小于 5 ns。有關(guān)相鎖定環(huán)路操作和應(yīng)用的更多信息，請(qǐng)參見 AND8040。 立即購買
    MC100EP140DGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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