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    首頁(yè)產(chǎn)品索引MC10E143

    MC10E143

    購(gòu)買收藏
    ?5.0 V ECL 9-Bit Hold Register

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10E/100E143 is a 9-bit holding register, designed with byte-parity applications in mind. The E143 holds current data or loads new data, with the nine inputs D0-D8 accepting parallel input data.
    The SEL (Select) input pin is used to switch between the two modes of operationHOLD and LOAD. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.
    The 100 Series contains temperature compensation.
    • 700MHz Min. Operating Frequency
    • 9-Bit for Byte-Parity Applications
    • Asynchronous Master Reset
    • Dual Clocks
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • 75k
    • Input Pulldown Resistors
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors
    • ESD Protection: > 2 KV HBM, > 200 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 484 devices
    • Pb-Free Packages are Available

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    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC10E143FNR2GONIC REGISTER HOLD 9BIT ECL 28PLCC 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載

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