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    首頁產(chǎn)品索引MC10E154

    MC10E154

    購買收藏
    1 Mux Latch

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10E/100E154 contains five 2:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output data is controlled by the multiplexer select control, SEL. A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
    The 100 series contains temperature compensation.
    • 850ps Max. LEN to Output
    • 825ps Max. D to Output
    • Differential Outputs
    • Asynchronous Master Reset
    • Dual Latch-Enables
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors
    • ESD Protection: > 2 kV HBM, > 200 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 237 devices
    • Pb-Free Packages are Available

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    型號制造商描述購買
    MC10E154FNGONIC MULTIPLEXER 5 X 2:1 28PLCC 立即購買

    技術(shù)資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載
    Interfacing with ECLinPSPDF72 點擊下載

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