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    首頁(yè)產(chǎn)品索引MC10EP52

    MC10EP52

    購(gòu)買收藏
    ?3.3 V / 5.0 V ECL Differential Clock/Data D Flip-Flop

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to V
    ) the outputs of the device will remain stable.
    • 330ps Typical Propagation Delay
    • Maximum Frequency > 4 GHz Typical
    • PECL Mode: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Q Output will default LOW with inputs open or at V
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC10EP52DTR2GONIC FF D-TYPE SNGL 1BIT 8TSSOP 立即購(gòu)買
    MC10EP52DGONIC FF D-TYPE SNGL 1BIT 8SOIC 立即購(gòu)買
    MC10EP52DTGON 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載
    Thermal Analysis and Reliability of WIRE BONDED ECLPDF119 點(diǎn)擊下載
    Clock Generation and Clock and Data Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Metastability and the ECLinPS FamilyPDF103 點(diǎn)擊下載
    Phase Lock Loop General OperationsPDF64 點(diǎn)擊下載
    3.3 V / 5 V ECL Differential Data and Clock D Flip FlopPDF183 點(diǎn)擊下載
    IBIS Model for mc10ep52dt 3.3VUNKNOW5 點(diǎn)擊下載
    SOIC-8 Narrow BodyPDF61 點(diǎn)擊下載

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