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    首頁(yè)產(chǎn)品索引MC74HC390A

    MC74HC390A

    購(gòu)買收藏
    ?Dual 4-Stage Binary Ripple Counter with ÷2 and ÷5 Sections

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    High-Performance Silicon-Gate CMOS
    The MC74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors,they are compatible with LSTTL outputs.
    This device consists of two independent 4-bit counters, each composed of a divide-by-two and a divide-by-five section. The divide-by-two and divide-by-five counters have separate clock inputs, and can be cascaded to implement various combinations of divide-by-2 and/or divide-by-5 up to a divide-by-100 counter.
    Flip-flops internal to the counters are triggered by high-to-low transitions of the clock input. A separate, asynchronous reset is provided for each 4-bitcounter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A.
    • Output Drive Capability: 10 LSTTL Loads
    • Outputs Directly Interface to CMOS, NMOS, and TTL
    • Operating Voltage Range: 2 to 6 V
    • Low Input Current: 1
    • A
    • High Noise Immunity Characteristic of CMOS Devices
    • In Compliance with the Requirements Defined by JEDEC Standard No 7A
    • Chip Complexity: 244 FETs or 61 Equivalent Gates
    • Pb-Free Packages are Available*

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    NLV74HC390ADR2GON 立即購(gòu)買
    MC74HC390ADTR2GON 立即購(gòu)買
    MC74HC390ADGON 立即購(gòu)買
    MC74HC390ADR2GON 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    Dual 4-Stage Binary Ripple Counter with Divide-By-2 and Divide-By-5 SectionsPDF121 點(diǎn)擊下載
    SOIC 16 LEADPDF37 點(diǎn)擊下載
    SOIC-20 WBPDF35 點(diǎn)擊下載
    TSSOP-16PDF40 點(diǎn)擊下載
    MC74HC390A_PKG.GIFUNKNOW9 點(diǎn)擊下載

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