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    首頁產(chǎn)品索引NB3RL02

    NB3RL02

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    ?Clock Fanout Buffer, 2-Channel, Low Phase Noise

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The NB3RL02 is a low-skew, low jitter 1:2 clock fan-out buffer, ideal for use in portable end-equipment, such as mobile phones. With integrated LDO and output control circuitry. The MCLK_IN pin has an AC coupling capacitor and will directly accept a square or sine wave clock input, such as a temperature compensated crystal oscillator (TCXO). The minimum acceptable input amplitude of the sine wave is 300 mV peak-to-peak. The two clock outputs are enabled by control inputs CLK_REQ1 and CLK_REQ2. The NB3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3 V to 5.5 V and outputs 1.8 V at Iout = 50 mA. This 1.8 V supply is externally available to provide regulated power to peripheral devices, such as a TCXO. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The NB3RL02 is offered in a 0.4 mm pitch wafer-level-chip-scale (WLCS) package (0.77 mm x 1.57 mm) and is optimized for very low standby current consumption.
    • Low Additive Noise: -149 dBc/Hz at 10 kHz Offset Phase Noise
    • Regulated 1.8 V Output Supply Available for External Clock Source,
    • ie. TCX0
    • Ultra-Small Package: 8-ball: 0.4 mm Pitch WLCS (0.77 mm x 1.57 mm)
    • ESD Performance Exceeds JESD 22: 2000 V Human Body Model

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    型號(hào)制造商描述購買
    NB3RL02FCT2GON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    WLCSP8 1.57x0.77PDF29 點(diǎn)擊下載
    Low Phase-NoiseTwo-Channel Clock Fanout BufferPDF94 點(diǎn)擊下載

    應(yīng)用案例更多案例

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